1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a designing method of an interconnection thereof, and more particularly to a semiconductor integrated circuit using a core macro comprising a plurality of circuits, such as a CPU incorporating peripheral circuits such as a DMA controller, an interruption controller, a timer/counter, a local bus(arbiter, a clock oscillator or the like, and a designing method of an interconnection thereof.
2. Description of the Related Art
FIG. 1 is a top view showing one example of a conventional semiconductor integrated circuit incorporating a core macro. In FIG. 1, a chip 418 is a semiconductor integrated circuit which is provided with a core macro 419 and which is connected with a signal interconnection 420. The core macro 419 is registered as an interconnection inhibition area so that the signal interconnection does not pass thereon.
Next, the designing method of an interconnection of this semiconductor integrated circuit will be explained hereinafter.
In the case where the chip 418 is laid out, the core macro 419 is arranged in the beginning. After that, the signal interconnection 420 is connected in an automatic interconnection. Since the core macro 419 is registered as an interconnection inhibition area in the automatic interconnection, the signal interconnection 420 is connected by making a detour around the core macro 419.
In the aforementioned interconnection method, there is a problem in that since the signal interconnection which makes a detour is concentrated around the core macro 419, the area of the chip 418 is increased.
As a method for improving the aforementioned problem, there is provided an art which is disclosed in Japanese Patent Application Laid-Open No. 5-109892. The art which is disclosed in the aforementioned JP-A will be explained hereinafter.
FIG. 2 is a flowchart showing an automatic interconnection processing for preventing an increase of the chip area which is disclosed in the aforementioned JP-A.
First of all, an outline interconnection processing 522 which takes in consideration the passing interconnection on the core macro will be carried out. Next, on the basis of the passage which is determined in the outline interconnection processing 522, a passage designation processing 523 will be carried out for extracting a partial passage of the outline interconnection passage which passes on the core macro for each of the core macros. Subsequently, with the interconnection processing 524 which passes on the core macro, a detailed interconnection corresponding to the partial passage which has been extracted in the passage designation processing 523 is carried out by using the interconnection which passes on the core macro. In the passage interconnection processing 524 on the core macro, the interconnection layer which is not used at the time of layout design in the core macro is primarily used. After that, a confirmation processing 525 is carried out to confirm whether or not the passage interconnection processing on the core macro has been terminated with respect to all the core macros. When the processing has not been terminated with respect to all the core macros, the process is brought back to the passage interconnection processing 524 on the core macro to carry out the processing with respect to all the core macros which are not processed. In the case where the processing has been terminated with respect to all the core macros, the interconnection processing 526 between channels on the chip level has been carried out thereby terminating a layout design.
FIG. 3 is a top view showing one example of the outline interconnection passage in which the passage interconnection on the core macro has been considered. It is considered that the example shown in FIG. 3 will be laid out. On the chip 626, three core macros 627, 628 and 629 are arranged. The outline interconnection passage which is shown by a dot line with respect to an actual terminal shown by X is considered as passage information.
In the beginning, as an advance processing, a net list which passes through each core macro is extracted from the passage information and is shown as a pin pair collection. In correspondence to this net list, as shown in FIG. 4, a temporary terminal 701 is provided on an external form of each of the core macros.
Next, as shown in FIG. 5, an interconnection is provided on the core macro on the basis of the net list for the passage on the core macro and information for controlling the passage route on the core macro.
Lastly, with respect to each pin pair on which a passage interconnection is successfully provided on the core macro, the temporary terminal 801 is converted into an actual terminal to determine a net list between the core macros.
It becomes possible to reduce the chip area by using the upper part of the core macro as an interconnection area from the aforementioned interconnection method.
However, in the conventional technique which has been described above, the number of interconnections which pass on the core macro for each of the chip layout, and the interconnection passage are different for each of the chip layouts, it becomes necessary to re-create the delay library of the core macro itself under the influence of the adjacent design or the crossing of the passage interconnection. From this point, the following problem will be generated.
The first problem is that when the upper part of the core macro constitutes an interconnection inhibition area in the layout of the chip which incorporates the core macro, the interconnection must be provided by making a detour around the interconnection inhibition area so that the chip area is increased.
The second problem is that it becomes necessary to change a delay library of the core macro for each of the layouts because the signal interconnection in the core macro is affected by the potential of the signal so that the AC characteristic of the core macro is changed when the interconnection is provided by using an empty area on the core macro at the time of the layout.